Swiss Federal Institute of Technology Lausanne, EPFL

Towards elevated-temperature (>2 K) monolithic quantum computing processors in production FDSOI CMOS technology

CityLausanne, Lake Geneva region, Switzerland
Date Monday, -
Institute of Microengineering - Distinguished Lecture

Campus Lausanne BM 5202 (live)
Campus Microcity MC B0 302 (video)
Zoom Live Stream :

Abstract: Universal quantum processors (QPs) "can now perform computations in a Hilbert space of dimension 253 ? 9 × 1015, beyond the reach of the fastest classical supercomputers available today." Despite reaching this crucial milestone, they remain expensive, difficult-to-scale, room-size, laboratory devices that operate at extremely low temperature, require many hours of tweaking before use, and can only run simple quantum algorithms of limited practical use. Their core building block, the qubit, is based on exotic superconducting Josephson-junction technology and is controlled by racks of electronic equipment connected through long coaxial cables. For the next phase of QP development where real-world problems can be solved, solutions must be found to ensure QP (i) scalability to millions of qubits, (ii) high fidelity (accuracy), (iii) reliability, (iv) low-cost, low-variability, high-yield volume manufacturing, and (v) ease and speed of testability.
To address the scalability, reliability, and manufacturing challenges, we propose to use the minimum-size transistor of production CMOS technology as the quantum processor qubit. This was not possible in the past due to large transistor dimensions but has become feasible in 22nm (Fully-Depleted Silicon on Insulator) FDSOI CMOS. The prospect of cheap quantum information processing in "plain old CMOS" is potentially revolutionary, since most other alternative proposals require fairly exotic technologies that lack scalability, high yield, reliability and low variability, and are difficult to interface with classical processors. It takes advantage of the the natural progression of Moore’s law to nanoscale dimensions and the transition from classical to quantum MOSFET behaviour.
This presentation will discuss the fundamental concepts and the feasibility of high-temperature (2-12 K) quantum processors, based on heterostructure Si1-xGex/Si1-yGey hole-spin qubits, monolithically integrated with control and readout electronics in commercial 22nm FDSOI CMOS technology. These temperatures, while still low, are 100 times higher than those of current competing quantum processors. Operation temperature is important because the QP is placed in a cryostat whose thermal lift (capacity to remove heat) increases exponentially with temperature.  Monolithic integration improves quantum processor fidelity, allows for scalability and ease of testability, reduces power consumption and cost, and improves manufacturability, yield and reliability.
The beneficial aspects of the SiGe channel hole-spin qubit will be emphasized in comparison with its silicon-only electron-spin counterpart. It will also be shown that, at 2-12 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.
Irrespective of the qubit technology, the development of large quantum processors is limited by the power consumption and associated heat dissipation of the analog-mixed-signal control and readout electronics and by the challenge of interconnecting such a large number of qubits with the control electronics. By developing elevated-temperature qubits, the heat dissipation constraints on the co-integrated or co-located control electronics and on the cryostat thermal lift are relieved, thus allowing for the integration of more complex quantum processors.
However, elevated-temperature qubits require higher-frequency spin control electronics, in the upper millimetre-wave and even THz frequency range. The design of low-power millimetre-wave spin manipulation electronic circuits will also be covered.  Finally, I will present measurements for full technology characterization at cryogenic temperatures up to 67 GHz and describe a methodology for cryogenic mm-wave control electronics design based on room-temperature transistor models.

Bio: Sorin P. Voinigescu is a Professor  in the Electrical and Computer Engineering Department at the University of Toronto where he holds the Stanley Ho Chair in Microelectronics and is the Director of the VLSI Research Group. He is an IEEE Fellow and an expert on millimeter-wave and 100+Gb/s integrated circuits and atomic-scale semiconductor device technologies. He obtained his  PhD degree in Electrical and Computer Engineering from the University of Toronto in 1994 and his  M.Sc Degree in Electronics and Telecommunications from the Politechnical Institute of Bucharest in 1984.

Note: The Seminar Series is eligible for ECTS credits in the EDMI doctoral program

Note: After the lecture, there will be time for discussion and interaction with the distinguished speaker, sandwich lunch and refreshments sponsored by the Institute of Microengineering will be provided for attendees in front of the lecture hall (BM 5104, ca. 13h15)


  • Institute of Microengineering


  • Niels Quack (Organizer)
    Sandro Carrara (Organizer)
    Edoardo Charbon (Host)

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  • EPFL CH-1015 Lausanne
  • 0041 (0)21 693 11 11

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